Vol. 5 No. 2 (2021)

Implementation Of Low Power Based Concurrent Error Detectable Carry Select Adder With Testability Technique

Published 2021-07-21 — Updated on 2021-07-21



This Paper Proposes Concurrent Error Detectable Adder With Testability. The Proposed Adder Is Designed Using Multi-Block Carry Select Adder. An Output Of The Adder Is Obtained By A Fault Modeled As A Single Stuck-At Fault Can Be Find By Comparing The Predicted Parity Of The Sum With The Parity Of The Sum And Comparing The Duplicated Carry Outputs. The Adder Is Testable With Ten Input Patterns Under Single Stuck-At Fault. This Property Detection Of A Fault Before The  Occurrence Of A Second Fault Is Easier. The Concurrent Error Delectability To Detect Erroneous Results And The Easy Testability To Find A Fault During Functions Are Important For Realizing Reliable Systems. The Concurrent Error Delectability And The Testability Of The Proposed Adder Are Proved. A 32-Bit Adder Has Been Designed And Its Concurrent Error Delectability Covers 100% Test Coverage Through The 10 Patterns Has Been Confirmed By Fault Simulation.