Design, Development and Integration of AXI-4 On-Chip Bus for Core Based Fabless System on Chip (SoC)

Abstract

In this project we proposed the development of AXI-4 on-chip bus for Open POWER Processor Core A2O, so the processor can communicate to each and every peripheral through the bus. The sub blocks designed for AXI-4 are developed by modeling in Verilog HDL. The master and slave are integrated among peripherals in compliance to SoC. The peripherals connected to bus are selected by using FSM Methodology. AXI-4 supports 16 masters and 16 slaves interfacing, with single master single slave talking to each other at a time.